Open to engineering internships
I write the layer most people import. — Sudip Paudel, Computer Engineer
Register-level firmware on ARM Cortex-M4, synthesised SystemVerilog on FPGA, and two platforms running in production. Computer Engineering at UT Arlington.
- Based in
- Euless, TX
- Focus
- Embedded · Hardware · Full-stack
Selected work
Engineering projects: embedded firmware, FPGA RTL, full-stack
IR Remote Control Replacement
Embedded · 2025
A bare-metal universal IR remote that records and replays signals from any consumer remote via a UART command shell — every driver written at the register level, with no vendor HAL.
- 2025IEEE 754 Half-Precision Floating-Point AdderSystemVerilog · Intel Quartus Prime · Static timing analysisSystemVerilog · Intel Quartus Prime · Static timing analysisFPGA / RTL
- 2025AntarLensNext.js · React · Supabase (Postgres, RLS)Next.js · React · Supabase (Postgres, RLS)Full-Stack
- 2025KashllyNext.js · React · SupabaseNext.js · React · SupabaseFull-Stack
- 2024Network Security ProjectNetwork security · Threat modeling · Team leadershipNetwork security · Threat modeling · Team leadershipSecurity
About
About Sudip Paudel, computer engineer
Most of my work happens a layer below where people usually start.
On the TM4C123 I write the clock, UART, timer and NVIC setup myself, straight out of the datasheet, rather than calling TI's HAL. It takes much longer to get anything working. It also means that when something breaks I know which register I got wrong. FPGA work runs on the same instinct in SystemVerilog: I pay more attention to the timing report than the simulation waveform, because a design can simulate perfectly and still fail to close.
I write web software too. AntarLens and Kashlly are both live, and I built each one end to end: schema, auth, the product, the deploy. On AntarLens the user isolation lives in Postgres row-level security instead of route handlers, so a bug in my own code can't hand one person's data to somebody else.
I'm at UT Arlington studying Computer Engineering. Open to internships or roles close to the hardware, the systems, or both.
Capability
Technical skills: languages, embedded hardware, tools
Languages
Roughly in order of how much I've written
- C
- C++
- SystemVerilog
- Assembly (ARM)
- Java
- JavaScript / TypeScript
- SQL
- HTML / CSS
Embedded / Hardware
Parts, instruments, and the layer below the OS
- ARM Cortex-M4 (TM4C123)
- Register-level drivers
- Timers & input capture
- PWM / UART / NVIC
- Intel MAX 10 FPGA
- Static timing analysis
- Raspberry Pi / Embedded Linux
Tools & Platforms
Toolchains and infrastructure
- TI Code Composer Studio
- Intel Quartus Prime
- Git / Linux
- Next.js / React
- Node.js
- Supabase (Postgres, RLS)
- OpenAI API
- Vercel
Education
Education: B.E. Computer Engineering, UT Arlington
Expected May 2027
University of Texas at Arlington
B.E., Computer Engineering · Arlington, TX
Digital Logic, Embedded Systems, Computer Architecture, Operating Systems, Electronics & Circuit Analysis, C Programming
May 2024
Dallas College
Associate of Science · Dallas, TX
Contact
Contact Sudip Paudel, computer engineer
Open to engineering work across embedded, hardware and full-stack. Email me directly or use the form.